1. Field of the Invention
This invention relates to semiconductor devices and, more particularly, to a method for connecting the devices on an integrated circuit substrate to a metallization layer.
2. Description Of The Relevant Art
Many techniques are known for connecting features on an integrated circuit substrate, such as the source, drain, and gate of MOS transistors or the emitter, base, and collector of bipolar transistors, to a metallization layer, or for connecting two successive metallization layers in a multi-level interconnect scheme. One such technique uses etched contacts and vias which require successive placement of metal and dielectric layers over the substrate features, resulting in very uneven surfaces. Planarization of the interlevel dielectric layer to smooth the surface results in contact holes of different depths which cause difficulties in etching, such as prolonged overetch of certain features in the substrate. Another technique uses metal pillars in place of etched contacts and vias. This scheme offers the advantages of higher device packing density and smooth, planar surface topography. To form the pillars which connect the devices formed in the substrate to metallization layers above the substrate, the pillar metal layers typically are deposited in the appropriate sequence directly on top of the features on the wafer. These features include junction and electrode areas (possibly silicided), oxide and trench isolation features, oxide spacers around certain features, etc. After pillar metal deposition and lithography, the metal layers are dry-etched from top to bottom, i.e., down to the aforementioned features in the substrate. The substrate features thus are exposed again at the end of metal pillar definition. If the dry etch selectivity between the bottom pillar metal layer (which may be an etch-stop/diffusion barrier layer consisting of titanium and tungsten, either as an alloy or separate layers) and any of the exposed materials on the substrate (e.g., silicon or titanium silicide) is poor, the bottom metal layer must be wet-etched in a suitable solution (e.g., a mixture of hydrogen peroxide and ammonium hydroxide), which affords good selectivity to all the exposed materials on the substrate.
There are several disadvantages associated with this procedure for defining the metal pillars. For example, the non-uniformity of dry-etch rate across a wafer or from wafer to wafer in a batch of wafers etched together sometimes results in a significant erosion of the etch-stop layer during the dry-etch process, and this results in attack on any inadvertently exposed features on the substrate. The glow discharge radiation from the dry-etch process also can damage the exposed devices. Furthermore, the abrupt topography of some features in the substrate, such as polysilicon gates of MOS transistors, leads to poor coverage of the metallization layer over the steps formed by such features. Voids or cracks are sometimes observed in the metal layer covering the steps, and these voids and cracks can grow larger during subsequent processing, e.g., during lithography. During the pillar metal-etch, such voids or cracks can result in a substantial attack on the exposed substrate. Finally, unevenness in the substrate features also frequently leads to the formation of metal residue ribbons or stringers along steep edges of the features, as well as metal residue in the narrow spaces between the pillars and adjacent substrate features (e.g., polysilicon gates). Both defects cause undesirable electrical shorting.
For additional background information on the foregoing, see MULTILEVEL METALLIZATION WITH PILLAR INTERCONNECTS AND PLANARIZATION, EGIL D. CASTEL, VIVEK D. KULKARNI, AND PAUL E. RILEY, PROCEEDINGS OF THE FIRST INTERNATIONAL SYMPOSIUM ON ULTRA-LARGE SCALE INTEGRATION SCIENCE AND TECHNOLOGY, VOL. 87-11, THE ELECTROCHEMICAL SOCIETY, 1987, and references cited therein, all of which are incorporated herein by reference.